SINV=0, CHR1=0, SDIR=0, BCP2=0, SMIF=0
Smart Card Mode Register
| SMIF | Smart Card Interface Mode Select 0 (0): Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) 1 (1): Smart card interface mode |
| Reserved | This bit is read as 1. The write value should be 1. |
| SINV | Transmitted/Received Data Invert Set this bit to 0 if operation is to be in simple I2C mode. 0 (0): TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1 (1): TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. |
| SDIR | Transmitted/Received Data Transfer Direction NOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode. Set this bit to 1 if operation is to be in simple I2C mode. 0 (0): Transfer with LSB first 1 (1): Transfer with MSB first |
| CHR1 | Character Length 1 (Only valid in asynchronous mode) 0 (0): Transmit/receive in 9-bit data length 1 (1): Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) |
| Reserved | These bits are read as 11. The write value should be 11. |
| BCP2 | Base Clock Pulse 2 Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits 0 (0): S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) 1 (1): S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) |